A variety of means and techniques are known for generating a local clock signal by locking to an incoming data signal. In U.S. Pat. No. 4,677,648 of Zurfluh a digital phase locked loop is disclosed wherein a chain of delay elements implements phase offset detection and clock signal phase shifting. The system requires continual estimation of the number of delay elements in a delay element string for a delay time equal to one period of the local clock and a look-up table is required to correct the phase offset to a phase selection value.
In U.S. Pat. No. 4,868,514 of Azevedo et al a digital phase locked correction loop is reset by subtracting one local clock cycle whenever the buildup of successive delay increments added to the system clock equals a full local clock cycle.
In U.S. Pat. No. 4,972,444 of Melrose et al, a digital phase locked device includes registers, triggered during successive selection cycles by a clock sequence generator, which trap the states of waveforms supplied by a delay element string. A transition detector detects transitions in the trapped waveforms and provides output bit patterns corresponding with the clock position. The system provides means for switching from a startup mode, which identifies a window and selects a bit pattern within the window, to a locked mode, in which bit patterns are continuously monitored for positioning within the window, to an unlocked mode and return to the startup mode when error logic indicates consecutive errors due to successive bit patterns that are outside the window. The system of Melrose et al also uses the clock sequence generator for generating signals defining a selection cycle during which the various other operations are performed.
While the prior devices operate satisfactorily, they are too slow for certain high speed serial data buses such as fiber optic buses where a short preamble is used. To be fast enough for such an application, the clock recovery circuit must be able to lock on to the incoming serial data stream as fast as possible. Specifically, it was desired that the circuitry be able to lock onto the binary serial data stream within seven rise time transitions. In addition to the initial synchronization, the circuit must also track and adjust the clock during the reception of the message frame. Most digital PLLs are slow and require at least 10 bit transitions of the incoming data to lock phase with the local clock. Prior PLL implementations employ elaborate clock selection algorithms and complex control circuitry. The design must utilize an all digital technique which is independent of the implementation technology.